Semiconductor integrated circuit devices, such as dynamic random access memory (DRAM) devices, undergo a tremendous amount of testing at various steps in the production process. Typically, DRAM devices are tested by using write and read operations to determine whether all of the cells of the memory array can properly store data signals and whether the data signals can be read out of the memory array. As memory chips become more dense, the testing time that is required to verify that data is being correctly stored and read out has increased dramatically.
In one test that is commonly used to identify faulty cells of a memory array, a signal having a logic level of either one or zero is applied to one group of the memory cells and signals of the opposite logic level are applied to the remaining cells. The signals are then read out of the cells individually and tested for the correct logic levels. This test must be repeated for each of the cells in the memory array and the entire procedure is repeated with signals of the opposite logic levels. Consequently, testing an array of memory cells requires a substantial amount of time.
Another procedure for testing memory cells in DRAM devices employs static refresh testing to identify faulty cells of the memory array. In this procedure, each memory cell is refreshed during a refresh cycle of a specified time interval. After the refresh operation has been completed, the data that is stored in all of the memory cells is checked to identify memory cells that failed to hold the stored data. Typically, such memory test requires 300 milliseconds of static refresh time for each memory cell depending on the value of the substrate voltage.
Consequently, the test time for a single memory chip can be excessive and when several hundred such chips on a wafer are tested sequentially the test time is considerable. When one considers the millions of parts that must be tested each month, the end result will be significant in terms of time spent and in terms of increase in time to market. The requirement that solid state memory devices be tested exhaustively, and the time required to perform these tests, greatly impact on the cost of the semiconductor devices. Therefore, it would be in the best interest of the semiconductor manufacturers to reduce the test time without compromising the quality of the tests.
A key indicator for margin quality of a semiconductor integrated circuit devices is the divide Vcc by two (DVC2) voltage margin for the integrated circuit devices. Accordingly, this indicator frequently is tested to insure quality of DRAM devices. For a DRAM device, the DVC2 margin is tested by increasing the voltage DVC2 to test for a logic 1 level margin and by lowering the voltage DVC2 to test for the logic 0 level margin. The margin test is generally run on packaged circuits. In many cases, this margin test procedure is conducted by hand, which is a very time intensive process. Because the voltage DVC2 is not bonded out to an external pin, the package has to be removed first before the test can even be started. Consequently, there is a high risk that the semiconductor device may be damaged during the testing process or in removing the packaging for conducting the margin test.
Accordingly, procedures have been developed, although not universally accepted. In one arrangement disclosed in U.S. Pat. No. 5,212,442, access is made to the DVC2 generator to permit the value to be changed. This arrangement uses a test vector and causes the substrate bias voltage generator to set the substrate bias voltage Vbb at ground or to be disabled. Another arrangement provides for setting the substrate voltage Vbb at ground or at a level that is more negative than ground. The negative voltage is applied by using an external pin, such as the pin by which a chip select signal is applied or the pin by which the output enable signal is applied. One shortcoming of this arrangement is that tests that require memory read or write operations cannot be performed when externally forcing either of these pins.
Another arrangement which is provided in a 256×16 DRAM memory device, commercially available from Micron Technology, Inc. as part number MT4C 16256, includes a test circuit that provides for selection of internal voltages such as the substrate bias Vbb, the wordline bias voltage Vccp, the cellplate bias or digitline equilibrating voltage DVC2. The test circuit includes that provides for setting the voltage Vbb at ground or at a more negative voltage, in the manner of the test circuit disclosed in U.S. Pat. No. 5,212,442, that is referenced above. In addition, the test circuit sets the voltage Vccp on or off. The test circuit provides the voltage DVC2 at a normal level, and setting it up to one higher value DVC2 up or down to one lower value DVC2 down.
A further goal of semiconductor manufacturers is to maximize yield. As technology advances decrease the feature size of the semiconductor elements and demands are made to increase the capacity of the memory array, the memory is more prone to defects that damage memory cells of memory devices. Typical memory device repair is accomplished by supplying a few redundant rows or/and columns, which are substituted for failed rows or columns of the memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved method and voltage generating circuit for allowing packaged part testing of semiconductor integrated circuits to confirm proper operation of the circuits and to reduce the time that is required to perform the testing of the integrated circuit devices.